|RE: DFA Scheduler and Processor Pipelines firstname.lastname@example.org (Naveen Sharma, Noida) (2002-05-04)|
|From:||"Naveen Sharma, Noida" <email@example.com>|
|Date:||4 May 2002 14:22:20 -0400|
|Posted-Date:||04 May 2002 14:22:20 EDT|
> well this is a really very unknown part for me. Does anyone know
> what exactly a DFA Scheduler is, or even how to implement such a
It is a scheduling technique based on FINITE AUTOMATA
Efficient Instruction Scheduling using Finite State Automata
by Vasanth Bala and Norman Rubin. (MICRO-28) Nov,95
Broadly speaking GCC had function unit based model for
scheduling in which described characterisitics of
processor unit in the pipeline (multiplicity,simultaneiuty etc).
This is based the other way round. Instruction are described
in terms of functional unit requirements. The scheduler
maintains a collision matrix for resource hazards in processor pipeline
(which corresponds to a DFA state) and updates it as insns are issued.
Incidentally I wrote DFA description for Sh4 processor for GCC and
this method would yield performance improvement of the
order of 10-18 %
You will get lot more detail in the research paper which
is downloadable from the net.
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