Hardware Bounds Checking

Pramod Ramarao <pramod@linux-1.ee.iastate.edu>
6 Apr 2002 23:17:36 -0500

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Related articles
Hardware Bounds Checking pramod@linux-1.ee.iastate.edu (Pramod Ramarao) (2002-04-06)
Re: Hardware Bounds Checking nmm1@cus.cam.ac.uk (2002-04-07)
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From: Pramod Ramarao <pramod@linux-1.ee.iastate.edu>
Newsgroups: comp.compilers
Date: 6 Apr 2002 23:17:36 -0500
Organization: Iowa State University, Ames, Iowa, USA
Keywords: errors, architecture
Posted-Date: 06 Apr 2002 23:17:36 EST

Hello everyone,
Sometime back, there was a lengthy discussion about this topic on
comp.compilers. One of the guys mentioned about the Unisys A-series
mainframe capable of performing bounds checking in hardware using a
structure called Actual Segment Descriptor(ASD). ASD contains the base
address, length and type of the array.
I was wondering as to how the ASDs are actually filled with the
corresponding data? Doing so with the compiler(obviously) would lead to a
performance degradation but they claim a low performance overhead. Am I
missing something?

Also, could a vairant of this scheme also be adopted to present
superscalar processors with low overhead?

Finally, could someone point me to the technical documentation of the
Unisys A-series architecture..it seems to have been removed from Unisys's



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