|Re: Possible data allocation and instruction scheduling algo... email@example.com (Mihai Christodorescu) (2002-01-24)|
|From:||Mihai Christodorescu <firstname.lastname@example.org>|
|Date:||24 Jan 2002 16:11:29 -0500|
|Posted-Date:||24 Jan 2002 16:11:20 EST|
On 24 Jan 2002, Orlando Llanes wrote:
> The way we got from the stalled code to the more optimal code was by
> moving instructions up as far as possible while considering each
> instruction's constraints.
Processors already do this in hardware, in the fetch-schedule
cycle(s). Search for reorder buffer, for example. The downside of
doing this in the processor is that the instruction window (the
sequence of instructions analyzed for possible code motion) is fixed
and usually fairly small.
Compilers also perform this kind of optimizations, and it is
the key component of instruction scheduling, AFAIK. I think that the
idea of "register status" that you suggested corresponds to live range
analysis. This is huge topic for research: on one hand small live
ranges simplify register allocation (and minimize the need for spills
to memory - significant for IA-32, not that much for IA-64?), on the
other hand the reordering to prevent stalls tends to make live ranges
bigger (since the way to prevent/reduce stalls is to move a register
write as far away from the register's next use).
Mihai Christodorescu -=- email@example.com - http://www.cs.wisc.edu/~mihai
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