|Makefile questions Stanya@aol.com (2001-07-03)|
|Re: Makefile questions firstname.lastname@example.org (Matthew J. Lockner) (2001-07-06)|
|Re: Makefile questions email@example.com (Wim Yedema) (2001-07-06)|
|Re: Makefile questions firstname.lastname@example.org (Marc Britten) (2001-07-06)|
|Re: Makefile questions email@example.com (walter) (2001-07-06)|
|Re: Makefile questions firstname.lastname@example.org (Lex Spoon) (2001-07-17)|
|From:||Wim Yedema <email@example.com>|
|Date:||6 Jul 2001 16:27:55 -0400|
|Posted-Date:||06 Jul 2001 16:27:55 EDT|
Stanya@aol.com (Stan) writes:
> What I need to do is figure out which files in the project are used
> for which applications -
can you call make for each separate application? if so you can just type
"make target" and look at the generated object files (assuming you generate
them) If you don't want to wait that long, GNU make has a -t option that
only touches files instead running commands, might be useful.
another possibility: run "nm" on the binary, this gives you the functions
and global variables that are used, then use something like TAGS to find
them in the sources.
it's a bit sketchy, but maybe it'll help.
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