|Testing the performance of Instruction Scheduler. email@example.com (phani narasimhan venkata sesha myreddy) (2000-11-09)|
|Re: Testing the performance of Instruction Scheduler. firstname.lastname@example.org (2000-11-09)|
|Re: Testing the performance of Instruction Scheduler. email@example.com (2000-11-11)|
|Re: Testing the performance of Instruction Scheduler. Sid-Ahmed-Ali.TOUATI@inria.fr (Sid Ahmed Ali TOUATI) (2000-11-11)|
|Re: Testing the performance of Instruction Scheduler. firstname.lastname@example.org (2000-11-16)|
|Date:||16 Nov 2000 14:59:54 -0500|
|Organization:||University of WI, Madison -- Computer Sciences Dept.|
|Posted-Date:||16 Nov 2000 14:59:53 EST|
phani narasimhan venkata sesha myreddy <email@example.com> wrote:
> Is there any tool to calculate the number of cycles taken by the code
> at run-time?
> Is there any tool to find for a specific run how many data cache
> misses have occured?
> Is there any tool that gives the number of pipiline stalls that have
> Is there any other way to look at the performance , apart from just
> comparing the execution times?
Sun has a tool called hstat which allows you to read and write
performance counters. You can use this to count cache and
pipeline activity. Beware that some counters in the UltraSPARC-II
are broken and need some workarounds to correctly calculate
some quantities (hstat comes with notes on how to do this). You
should be able to find hstat on Sun's web site somewhere, or
maybe ask the system admin to get hold of it.
There's also PCL (performance counter library) which is
a portable library to read/write performance counters and
has been ported to the SPARC. You can instrument your
generated code with calls to PCL to measure statistics for
interesting parts of your program. Again, beware that
some counters might be broken.
> How much performance gain one can expect from an instruction
If you can predict the cache behavior of your generated
code and schedule loads that can miss in the cache to be
far apart from the their first uses, you might see a big
win. I'm not sure if any other scheduling is worth it. The
UltraSPARC-II is an in-order statically scheduled processor
so it is more dependent on such scheduling than a out-of-order
processer such as the Pentium-III or Alpha.
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