|Compiler requirements...help needed email@example.com (Benedict, Neal A) (2000-11-01)|
|Re: Compiler requirements...help needed firstname.lastname@example.org (Sebastian Moleski) (2000-11-04)|
|Re: Compiler requirements...help needed email@example.com (Travers Naran) (2000-11-04)|
|Re: Compiler requirements...help needed firstname.lastname@example.org (Ronald Benedik) (2000-11-05)|
|Re: Compiler requirements...help needed email@example.com (Clark L. Coleman) (2000-11-07)|
|From:||"Clark L. Coleman" <firstname.lastname@example.org>|
|Date:||7 Nov 2000 13:06:12 -0500|
|Organization:||University of Virginia|
Ronald Benedik wrote:
> The newer Intel Processors have Performance Monitor Counters
>implemented. So the user can use them in optimizing L2 cache accesses.
>However there's no such feature for the L1 cache. I think it would
>improve the compiler if it optimizes not only the register pressure,
>but also for the L1 cache. I think that would be managable
>because of the limited size of the L1 cache.
There have been L1 cache counters for as long as there have been
performance counters in the Intel processors, going back to the 60 MHz
Pentium. Check out Appendix A of the P6 Family System Programmer's
Guide, section A.1, from
Look at counter 45H (hex value in counter select field.) This counter
is incremented every time a line is brought into the L1 D-cache.
University of Virginia
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