|SSA-form and cmove firstname.lastname@example.org (Tommy Hoffner) (2000-08-13)|
|Re: SSA-form and cmove email@example.com (Stephen Clarke) (2000-08-20)|
|Re: SSA-form and cmove firstname.lastname@example.org (Tim Harris) (2000-08-27)|
|Re: SSA-form and cmove email@example.com (2000-09-02)|
|Re: SSA-form and cmove firstname.lastname@example.org (2000-09-13)|
|From:||"Stephen Clarke" <email@example.com>|
|Date:||20 Aug 2000 23:58:32 -0400|
"Tommy Hoffner" <firstname.lastname@example.org> wrote in message
> The first apporoach will as I understand it work, but it will have to be
> expanded to a move and a cmove after register allocation with little or
> no hope of eliminating unnessecary introduced move instructions
> afterwards as well as risking the allocation of an extra register
This problem is very similar to having to cope with two-address target
instructions (where one of the operands is overwritten with the
result) - you want to assign the oldval and newval to the same
register if possible, in order to make the copy unnecessary. For
two-address instructions, there is a straightforward technique to
handle this during register coalescing that yields good results.
(Basically, as well as attempting to coalesce the source and dest of
copy instructions, you would also attempt to coalesce the oldval and
newval operands of cmove instructions. In the cases where the
coalescing was successful, the separate move instruction would not be
> Is there any other RISC instructions that is inherently none SSA?
> ( cmove cond, newval, result is per definition a possible second
> assignment to result, right?)
Conditional move is a special case of predicated instruction. For
ISAs that have general predication (i.e. conditional execution of any
instruction), the problem must exist on every instruction. Are there
compilers that use SSA and support general predication in the same
representation? What do the IA-64 compilers do?
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