|x86 code generation firstname.lastname@example.org (Nick Shaffner) (2000-06-14)|
|Re: x86 code generation email@example.com (2000-06-20)|
|Re: x86 code generation firstname.lastname@example.org (Juergen Kahrs) (2000-06-20)|
|Re: x86 code generation email@example.com (2000-06-20)|
|From:||firstname.lastname@example.org (Michael L. Ross)|
|Date:||20 Jun 2000 02:29:39 -0400|
John is correct - Intel publishes optimization guides for each of its
processors, that show the best code to generate for each
processor. That won't help you with compiler techniques such as
intermediate representation and register management, of
course. However, the optimization guides provide a starting point for
what you're aiming at. You can also get Intel's compilers, which will
give you a pretty good notion of the best code you can generate for
Beyond that, you want some way of representing the IA32's addressing
modes in your intermediate representation, and some notion of modeling
which registers are killed implicitly by various instructions.
A good starting point on the register allocation issue is "Global
Register Allocation Based on Graph Fusion", by Thomas Gross et. al.
The best intermediate representation is always a matter of opinion.
Since many IA32 instructions are two address form, if you only care
about IA32(Intel Architecture, 32 bit), you might try modeling it that
way, to make the translation in to machine code more natural.
Just some thoughts...
| Michael L. Ross
| EY2-03 5350 N.E. Elam Young Pkwy.
| Hillsboro, Or. 97124 Phone: (503)696-3794
| Disclaimer: Not speaking for Motorola
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